// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 .
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : cpu_interface.sv
// Author        : 
// Created On    : 2022-08-25 15:10
// Last Modified : 
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

`ifndef __CPU_INTERFACE_SV__
`define __CPU_INTERFACE_SV__

`timescale 1ns/1ps

interface cpu_interface(input clk, rst_n);

    logic [1 -1:0] CPU_CS_N;
    logic [1 -1:0] CPU_RD_N;
    logic [1 -1:0] CPU_WE_N;
    logic [16 -1:0] CPU_ADDR;
    logic [32 -1:0] CPU_WDATA;
    logic [32 -1:0] CPU_RDATA;
    logic [1 -1:0] CPU_RDY_N;

    logic CPU_RD_N_ff, CPU_WE_N_ff, CPU_RDY_N_ff;

    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            CPU_RD_N_ff <= 1'b1;
            CPU_WE_N_ff <= 1'b1;
            CPU_RDY_N_ff<= 1'b0;
        end
        else begin
            CPU_RD_N_ff <= CPU_RD_N;
            CPU_WE_N_ff <= CPU_WE_N;
            CPU_RDY_N_ff<= CPU_RDY_N;
        end
    end

	clocking drv @(posedge clk);
		default input #1ps output #1ps;
        output CPU_CS_N;
        output CPU_RD_N;
        output CPU_WE_N;
        output CPU_ADDR;
        output CPU_WDATA;
        input CPU_RDATA;
        input CPU_RDY_N;
        input CPU_RDY_N_ff;
	endclocking : drv
	modport pkt_drv (clocking drv);

	clocking mon @(posedge clk);
		default input #1ps output #1ps;
        input CPU_CS_N;
        input CPU_RD_N;
        input CPU_WE_N;
        input CPU_ADDR;
        input CPU_WDATA;
        input CPU_RDATA;
        input CPU_RDY_N;
        input CPU_RDY_N_ff;
	endclocking : mon
	modport pkt_mon (clocking mon);

	clocking ready_drv @(posedge clk);
		default input #1ps output #1ps;
        input CPU_CS_N;
        input CPU_RD_N;
        input CPU_WE_N;
        input CPU_ADDR;
        input CPU_WDATA;
        input CPU_RD_N_ff;
        input CPU_WE_N_ff;
        output CPU_RDATA;
        output CPU_RDY_N;
	endclocking : ready_drv
	modport pkt_ready_drv (clocking ready_drv);

endinterface

`endif
